1. Field of the Invention
The present invention relates to a semiconductor integrated circuit comprising flip-flop memory cells and, more particularly, to a semiconductor integrated circuit intended to allow enlargement of a write operation to the memory cells.
2. Description of the Prior Art
With the recent process miniaturization, it has become extremely difficult to design a memory cell having stable characteristics for a semiconductor integrated circuit comprising flip-flop memory cells, such as a static random access memory (SRAM), due to variations in the characteristics of individual transistors composing the memory cells, and to the lower power source voltages. As a result, a lower production yield of the semiconductor integrated circuit resulting from the degradation of the operation margins of the memory cells has presented a problem. The operation margins of the memory cells include a write margin showing the ease of writing during data writing, and a static noise margin which is a margin for noise during data reading or data holding. In general, the write margin and the static noise margin have contradictory characteristics such that, when one of the margins is to be satisfied, the other margin decreases.
In general, a memory cell in a 1-port SRAM is composed of six transistors. When a write access is made to a memory cell array composed of the memory cells of a plurality of SRAMs, the gate of the access transistor of the selected memory cell is made conductive with a word line, and data is written from a bit line into the memory cell. At this time, however, the access transistors of the non-selected memory cells connected to the same word line also simultaneously become conductive, so that charges for precharging to a power source level Vdd flow into the storage node on the Low-level side of a flip-flop in the memory cell. As a result, the problem arises that the potential on the low-level side increases in the memory cell with a small static noise margin to invert the flip-flop and destroy stored data. With the miniaturization of the process of a semiconductor integrated circuit, the static noise margin has tended to be smaller so that the problem mentioned above has become serious.
As a prior-art technology for solving the problem, there is a method which uses memory cells each in a 8-transistor configuration, performs a read operation in advance to each of the selected cell and the non-selected cells without discrimination therebetween, latches read data, and rewrites the same data to the cells to prevent data destruction (see, e.g., “2007 Symposium on VLSI Circuits Digest of Technical Papers”, pp. 256-257, which document is hereinafter referred to as Non-Patent Document 1). FIG. 4 shows a structure of a conventional semiconductor integrated circuit. FIG. 5 shows an operation timing diagram of the conventional semiconductor integrated circuit. Of the components shown in FIG. 4, those provided in a plurality of numbers are distinguished from each other by adding branch numbers to the ends of the reference numerals thereof (e.g., memory cells 210-1, 210-2, and the like).
In a memory cell array 200, a plurality of memory cells 210 are arranged in rows and columns. Each of the memory cells 210 has the same structure. The memory cell array 200 comprises pairs of word lines (a pair of RWL and WWL) placed correspondingly to the respective rows of the memory cells 210, read bit lines (RBL1 and RBL2) placed correspondingly to the respective columns of the memory cells 210, and pairs of bit lines (a pair of WBL1 and XWBL1, and a pair of WBL2 and XWBL2) placed correspondingly to the respective columns of the memory cells 210.
As shown in FIG. 4, each of the memory cells 210 is composed of eight transistors, which are PMOS transistor QP1 and QP2, and NMOS transistors QN1 to QN6.
The PMOS transistors QP1 and QP2, and the NMOS transistors QN1 and QN2 constitute a flip-flop for storing data.
The NMOS transistor QN3 has a drain connected to one of the pair of write bit lines (e.g., WBL1 in the memory cell 210-1). The NMOS transistor QN4 has a drain connected to the other of the pair of write bit lines (e.g., XWBL1 in the memory cell 210-1).
The NMOS transistor QN5 has a gate connected to one of the storage nodes of the flip flop, and the NMOS transistor QN6 has a gate connected to the read word line RWL such that data in the storage node is read into the read bit line (e.g., PBL1 in the memory cell 210, or RBL2 in the memory cell 210-2).
Inverters 220 are provided correspondingly to the respective columns of the memory cell array 200 to amplify and output data in the read bit lines corresponding to the columns. Specifically, the inverter 220-1 amplifies and outputs data in the read bit line RBL1, and the inverter 220-2 amplifies and outputs data in the read bit line RBL2.
Latch circuits 230 are provided correspondingly to the respective columns of the memory cell array 200, and connected to the read bit lines corresponding to the columns to hold read data. For example, the latch circuit 230-1 latches data in the read bit line RBL1 when a control signal DL is on a Low level.
Multiplexers 240 are provided correspondingly to the respective columns of the memory cell array 200 to select either of input data DIN and outputs of the inverters 220 corresponding to the columns based on column address signals. For example, the multiplexer 240-1 selects either of the input data DIN and the output DO1 (output of the latch circuit 230-1) based on a column address signal CA1.
Each of write circuits 250 is composed of AND circuits 251 and 252, and NMOS transistors QN10 and QN11. For example, in the write circuit 250-1, the AND circuits 251 and 252 receive an output DI1 and a write control signal WE. The NMOS transistor QN10 is controlled by an output of the AND circuit 251 to supply a ground level to the write bit line WBL1 or WBL2. The NMOS transistor QN11 is controlled by an output of the AND circuit 252 to supply the ground level to the write bit line XWBL1 or XWBL2.
A multiplexer 260 receives respective outputs DO1 and DO2 of the latch circuits 230-1 and 230-2, and outputs either of the outputs DO1 and DO2 as output data DOUT based on a column address signal CA.
An operation of the semiconductor integrated circuit shown in FIG. 4 will be described with reference to the operation timing diagram of FIG. 5.
In a non-selected state in which an access is not made to either of the memory cells 210-1 and 210-2, the read word line RWL, and the write word line WWL are each on the Low level, and the NMOS transistors QN3, QN4, and QN6 of the memory cells 210-1 and 210-2 are each non-conductive.
The write bit lines WBL1, WBL2, XWBL1, and XWBL2, and the read bit lines RBL1 and RBL2 are each charged to the power source level Vdd by a precharge circuit (not shown).
On the other hand, the write control signal WE, and the column address signals CA1, CA2, and CA are each on the Low level.
During a write cycle to the memory cell 210, the read word line RWL initially shifts from the Low level to a High level irrespective of in the write cycle. As a result, the NMOS transistors QN6 become conductive so that data stored in the memory cells 210-1 and 210-2 is read therefrom without discrimination between the selected memory cell and the non-selected memory cell. FIG. 5 illustrates the case where High data is stored in the storage nodes n1 (see FIG. 4), and the NMOS transistors QN5 are conductive.
Subsequently, charges on the read bit line RBL1 are discharged via the NMOS transistors QN5 and QN6, and the potential thereof gradually lowers from the level Vdd as the High level. Likewise, the read bit line RBL2 connected to the memory cell 210-2 is also discharged, or the potential thereof is maintained on the level Vdd in accordance with the stored data, though not shown in FIG. 5.
Subsequently, when the potential of the read bit line RBL1 reaches ½ Vdd as the threshold of the inverter 220, the level of the output DO1 is inverted to shift from the Low level to the High level.
Thereafter, the control signal DL shifts to the Low level to latch the levels of the output DO1 and DO2. At this time, the column address signal CA1 and CA2 are set to the High level and the Low level, respectively, and the multiplexer 240-1 corresponding to the memory cell 210-1 as the selected memory cell selects the input data DIN from between the input data DIN and the output DO1. As a result, the output DI1 is set to the Low level as the write level of the input data DIN. At the same time, the multiplexer 240-2 corresponding to the memory cell 210-2 as the non-selected memory cell selects the output DO2 from between the input data DIN and the output DO2. As a result, an output DI2 is set to the value of the output DO2.
Subsequently, an operation of rewriting the read data is initiated. That is, the write control signal WE shifts to the High level so that the output of the AND circuit 251 in the write circuit 250-1 corresponding to the memory cell 210-1 shifts to the High level. As a result, the NMOS transistor QN10 becomes conductive so that the write bit line WBL1 is discharged from the power source level Vdd to shift to a ground level. On the other hand, the write bit line XWBL1 is maintained on the level Vdd.
At the same time, the write circuit 250-2 corresponding to the memory cell 210-2 as the non-selected memory cell also operates to discharge the write bit line WBL2 or XWBL2.
Subsequently, the write word line WWL shifts to the High level to make conductive the NMOS transistors QN3 and QN4 of the memory cells 210-1 and 210-2. As a result, data in the write bit lines WBL1 and XWBL1 is written to the memory cell 210-1, while data in the write bit lines WBL2 and XWBL2 is written to the memory cell 210-2.
After the writing is completed, the write word line WWL shifts to the Low level, and the write control signal WE shifts to the Low level. As a result, the write bit lines WBL1, WBL2, XWBL1, and XWBL2 are each charged to the level Vdd by the precharge circuit (not shown).
Next, during a read cycle from the memory cell 210-1, only the read operation during the write cycle described above is performed, as shown in FIG. 5. That is, the read word line RWL shifts to the High level to read the data from the memory cells 210-1 and 210-2 into the read bit lines RBL1 and RBL2, and the multiplexer 260 outputs either of the outputs DO1 and DO2 latched by the lath circuits 230-1 and 230-2 to the outside in accordance with the value of the column address signal CA.
Thus, in the semiconductor integrated circuit shown in Non-Patent Document 1, the read operation is performed in advance even during the write cycle, and output data is latched in correspondence to each of the columns composing the memory cell array. Subsequently, either of the external input data and the read data is selected via the multiplexer, and then rewritten to the memory cells through the write circuits. As a result, even though stored data is destroyed by charges flowing from the write bit line connected to the non-selected memory cell into the memory cell node when the write word line is caused to shift to the High level, the data prior to the destruction can be rewritten. That is, with the semiconductor integrated circuit, it becomes possible to guarantee data in the non-selected memory cell.
However, the semiconductor integrated circuit described in Non-Patent Document 1 has the problem that, since the read operation needs to be performed in advance even during the write cycle, a write cycle time is elongated.
In addition, even during the write cycle, charging and discharging of the read bit lines is performed to perform the read operation. This leads to another problem of a larger consumed current than in an inherent operation which performs only data writing with the write bit lines.
There is still another problem of an area increase since the latch circuits and the multiplexer circuits need to be disposed correspondingly to the respective columns of the memory cells composing the memory cell array.